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Define ASIC/FPGA architecture |
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Define and verify methodology |
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Tool selection & set-up |
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Feasibility assessment |
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Specification assessment and feedback |
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Module level VHDL coding and verification |
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Top level simulations at Register Transition Level (RTL) and gate level |
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Simulate insertion and design for testability |
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Floor planning and optimization |
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Integration of Hardware/Software interface |
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Hardware/Software co-verification |
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Synthesis to target technology |
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FPGA prototyping |
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Synthesisable RTL coding in Verilog/ VHDL |
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Design for testing like boundary scan, internal scan, etc. |
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Formal verification |
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